1. Technical Field
Various embodiments relate to a semiconductor device and an operating method thereof, and more particularly, to an erase operation of a semiconductor device.
2. Related Art
A semiconductor device often includes a memory cell array, a circuit group and a control circuit. The memory cell array includes a plurality of memory blocks and is configured to store data. The circuit group is typically configured to perform one or more of program operations, read operations and erase operations associated with a selected memory block in the memory cell array. The control circuit is typically configured to control the operation of the circuit group.
In many cases, the control circuit is configured to issue commands to the circuit group to perform various operations based on one or more setting values associated with each of the operations.
For example, when an erase operation is performed on a selected memory block selected from among the plurality of memory blocks, an erase voltage Vera is applied to a well of the selected memory block. The threshold voltages of the memory cells are lowered by voltage differences between the memory cells in the selected memory block and a channel, and the erase operation is performed.
In many cases, an erase operation that employs an incremental step pulse erase (ISPE) method that gradually increases an erase voltage Vera is used. During the implementation of the ISPE method, a plurality of erase loops are repeatedly performed. Each of the erase loops includes the application of the erase voltage Vera to a well of the selected memory block, and determining whether the threshold voltages of the memory cells in the selected memory block has been lowered to a target level. Based on the determination, the erase voltage Vera may be increased by a constant step voltage Vstep if the erase loop is repeated. As shown in Table 1, the step voltage Vstep is typically maintained at a constant voltage and the erase voltage is incrementally increased by the constant step voltage Vstep with each repetition of the erase loop.
TABLE 1Erase loop countErase voltageVoltage difference1Vera2Vera + VstepVstep3Vera + 2VstepVstep4Vera + 3VstepVstep. . .. . .. . .k − 1Vera + (k − 2)VstepVstepKVera + (k − 1)VstepVstep